Journey
Semiconductors to synapses — one engineering path, two disciplines.
2025 – Present
Senior Design Engineer
Qualcomm
Working on hardware design for neural processors, focusing on RTL design, architectural optimization, and power-efficient compute systems.
2025 – Present
Independent Neurotechnology Research
Wearable EEG Sensing Platform
Developing a custom wearable platform for EEG and physiological signal acquisition, integrating custom electronics, embedded systems, wireless communication, and biosignal sensing.
2025 – 2026
Research Volunteer
University of Technology Sydney
Worked on EEG signal analysis with a focus on inter-subject variability. Implemented and evaluated meta-learning approaches to improve adaptability of EEG-based neural decoding models across subjects.
2024 – 2025
RTL Design Engineer
Qualcomm
2022 – 2024
M.S. Electrical Engineering
University of Washington
2023 – 2024
FPGA Design Engineering Intern
Intel
2023
RTL Design Engineering Intern
Qualcomm
2022 – 2023
Graduate Research Assistant
University of Washington
Supported neural engineering research involving brain-computer interfaces, including neural experiments, stimulation modeling, and computational analysis.
2020 – 2022
Design Verification Engineer
Qualcomm
2018 – 2022
Research Volunteer
Delhi Technological University
Conducted research on hardware-efficient arithmetic architectures, low-power circuit design, and FPGA-based implementations using Verilog HDL.
2016 – 2020
B.Tech Electronics and Communication Engineering
Delhi Technological University