Research
My research spans hardware systems, computational methods, and neural engineering.
Selected Publications
Meta-Learning for BCI: A Promising New Direction
2025 International Conference on Fuzzy Theory and Its Applications (iFUZZY)
Research Focus: EEG-based brain-computer interfaces, meta-learning, neural decoding
This work explores challenges in EEG-based brain-computer interfaces, including cross-subject variability, calibration requirements, and limited robustness outside controlled environments. It investigates meta-learning approaches, including Model-Agnostic Meta-Learning for EEG (MAML-EEG) and Adaptive Bayesian Meta-Learning (ABML), as potential approaches for developing more adaptive and scalable neural decoding systems.
Publication →Approximate Karatsuba Multiplier for Error-Resilient Applications
AEU – International Journal of Electronics and Communications, 2021
Research Focus: Approximate computing, arithmetic architectures, hardware optimization
This work explores approximate multiplication architectures using Karatsuba multiplication to reduce hardware utilization and latency while maintaining computational accuracy for error-resilient applications.
Publication →Hybrid Dynamic CML with Modified Current Source (H-MDyCML): A Low-Power Dynamic MCML Style
Advances in Electrical and Electronic Engineering, 2021
Research Focus: Low-power digital circuits, MOS current mode logic, circuit optimization
This work investigates a modified low-power MOS current mode logic architecture using a PMOS-driven dynamic current source and complementary pass transistor logic. The proposed H-MDyCML design demonstrates improvements in power-delay performance compared with existing current mode logic approaches.
Publication →FPGA Implementation of DHT Through Parallel and Pipeline Structure
2021 International Conference on Computer Communication and Informatics (ICCCI)
Research Focus: FPGA architectures, hardware acceleration, digital signal processing
This work presents FPGA implementations of the Discrete Hartley Transform using parallel and pipelined architectures. The proposed designs were implemented using Verilog HDL on a Zynq-based FPGA platform and evaluated for improvements in hardware utilization, power consumption, and computation latency.
Publication →Patents
A Race-Free Current Mode Logic (NORA-CML) System
Indian Patent No. 406525 · Issued September 13, 2022
This patent presents a race-free current mode logic architecture using cascaded PMOS and NMOS dynamic current mode logic modules. The proposed approach eliminates the need for intermittent self-timed buffer circuitry during cascading, enabling high-speed operation with reduced power dissipation and area utilization in multi-stage digital circuits.
Book
Dynamic Current Mode Logic: Concepts to Advancements
LAP Lambert Academic Publishing
This book provides an in-depth overview of MOS current mode logic circuits, covering fundamental concepts, modeling approaches, and design strategies for current-mode digital systems.
The book reviews different MOS current mode logic topologies and presents various dynamic and hybrid current mode logic architectures, including DyCML and H-DyCML structures. It further discusses their operating principles, design considerations, and comparisons for multi-level digital circuit applications.